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SMT-Based System Verification with DVF

12 pagesPublished: August 19, 2013


We introduce the <i>Deductive Verificaton Framework</i> (DVF), a language and a tool for verifying properties of transition systems. The language is procedural and the system transitions are a selected subset of procedures. The type system and built-in operations are consistent with SMT-LIB, as are the multisorted first-order logical formulas that may occur in DVF programs as pre- and post-conditions, assumptions, assertions, and goals. A template mechanism allows parametric specification of complex types within the confines of this logic. Verification conditions are generated from specified goals and passed to SMT engine(s). A general assume-guarantee scheme supports a thin layer of interactive proving.

Keyphrases: High-level modeling, SMT, system description languages, transition systems, verification

In: Pascal Fontaine and Amit Goel (editors). SMT 2012. 10th International Workshop on Satisfiability Modulo Theories, vol 20, pages 32--43

BibTeX entry
  author    = {Amit Goel and Sava Krstic and Rebekah Leslie and Mark Tuttle},
  title     = {SMT-Based System Verification with DVF},
  booktitle = {SMT 2012. 10th International Workshop on Satisfiability Modulo Theories},
  editor    = {Pascal Fontaine and Amit Goel},
  series    = {EPiC Series in Computing},
  volume    = {20},
  pages     = {32--43},
  year      = {2013},
  publisher = {EasyChair},
  bibsource = {EasyChair,},
  issn      = {2398-7340},
  url       = {},
  doi       = {10.29007/59rn}}
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