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Author:Rolf Drechsler

Publications
SAT Can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Luca Mueller and Rolf Drechsler
EasyChair Preprint 14322
Task Mapping and Scheduling in FPGA-Based Heterogeneous Real-Time Systems: a RISC-V Case-Study
Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler and Klaus McDonald-Maier
EasyChair Preprint 8979

Keyphrases

Arithmetic Circuits, FPGA, Heterogeneous embedded systems, Integer Linear Programming, Polynomial Formal Verification, RISC-V, SAT, Scheduling, time complexity, verification.

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