ITC INDIA 2025: 9th IEEE International Test Conference India 2025 Radisson Blu Bengaluru Outer Ring Road Bangalore, India, July 20-22, 2025 |
| Conference website | https://itctestweekindia.org |
| Submission link | https://easychair.org/conferences/?conf=itcindia2025 |
ITC India 2025
International Test Conference is the world's premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement.
At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.
For Authors
Authors are also invited to submit a single-page poster proposal, double-columned in Format (template available in EasyChair). Posters are a useful way of presenting late-breaking results, getting feedback on an innovative method, or participating without having to write a full paper.
Submission Guidelines
- An abstract of 100 words or less to be entered online
- An electronic copy of a complete paper up to 6 pages, double-columned in IEEE Format, A4 size to be submitted through EasyChair. Submissions less than 4 pages are rarely accepted.
- Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person
Committees
General Chairs
Sivanantham S, VIT Vellore
Gaurav Bhargava, Qualcomm, India
Technical Program Co-Chairs (TPC)
Kavitha Shankar, Nordic Semiconductor, UK
Subhadip Kundu, Qualcomm, India
Wilson Pradeep, Google, USA
Tutorial Co-Chairs
Bharath Nandakumar, Cadence, India
Lakshmanan Balasubramanian, Texas Instruments, India
Mehala Balasundaram, Synopsys, India
Abhishek Chaudhary, AMD, India
Industry Test Challenges Co-Chairs
Anuj Gupta, Cadence Design Systems
Nikhil Sudhakaran, Marvell, India
Industry Sessions Co-Chairs
Shamitha Rao, Synopsys
Sandeep Jain, Siemens EDA
Academia-Research Track Co-Chairs (ART)
Prof. Usha Mehta, Nirma University, Ahmedabad
Leela Krishna Thota, Synopsys, India
Prof. Binod Kumar, IIT Jodhpur
Test Reality Check Co-Chairs (TRC)
Rajit Karmakar, AMD, India
Veejaye Panayadian, Western Digital, India
Panel Chair
Kamlesh Pandey, Krivya Semicon, India
Posters Chair
Pranjal Giri, Texas Instruments, India
Publication Co-Chairs
Prof. R. Jayagowri, BMSCE, Bangalore
Prof. Sakthivel Ramachandran, VIT, Vellore
Fellowship Co-Chairs
Prakash Talawar, Western Digital, India
Prof.Saravanan P, PSG Tech, Coimbatore
Piyushkumar Chaniyara, Texas Instruments, India
Finance Chair
Krishnan Sreenivasan, AB Innovative
Communication/Website Co-Chairs
Nithin Bharadwaj, Microchip, UK
Abhirami R, Samsung Semiconductor India Research, India
Registration Chair
Leela Krishna Thota, Synopsys, India
Dharani Srinivasan, Qualcomm, India
Vikram, AMD, India
Marketing and Conference Management chairs
Veeresh Shetty, Siemens EDA
Samuel Dorairaj, Intel
TPC Advisory Committee
Prof. Alex Orailoglu, University of California, USA
Prof. James Chien-Mo Li, National Taiwan University, Taiwan
Dr.C.P. Ravikumar, India
R. D. (Shawn) Blanton, Carnegie Mellon University, USA
Contact
All questions about submissions should be emailed to
General Chairs
Sivanantham S, VIT Vellore (ssivanantham@vit.ac.in)
Gaurav Bhargava, Qualcomm (gauravb@qti.qualcomm.com)